1. Field of the Invention
The present invention relates generally to liquid crystal display devices and, more particularly, to effectual techniques adaptable for use with driver circuitry of a liquid crystal display device of the type which employs schemes for transferring a digital signal between drive circuits (drain drivers).
2. Description of the Related Art
Liquid crystal display modules of the type using super twisted nematic (STN) schemes or those of the thin-film transistor (TFT) type have been widely employed as display devices of notebook personal computers or else.
These liquid crystal display devices are typically designed to include a liquid crystal display panel and drive circuitry for driving the liquid crystal display panel.
And, in such liquid crystal display devices, one prior known device is disclosed in, for example, Japanese Patent Laid-Open No. 13724/1994, which is designed to input a digital signal (e.g., either display data or clock signal) only to a “top” driver circuit of multiple cascade-connected driver circuits while causing the digital signal to be sequentially transferred to the remaining driver circuits through inside of such driver circuits (this will be referred to as “digital signal sequential transfer scheme” hereinafter in the description).
While in the liquid crystal display device as taught from the above-identified Japanese document (Japanese Patent Laid-Open No. 13724/1994) semiconductor integrated circuit (IC) devices making up the driver circuitry are directly mounted on a glass substrate of the liquid crystal display panel, another liquid crystal display device of the type employing the above-noted digital signal sequential transfer scheme is also known, which is with semiconductor integrated circuit (IC) devices making up this driver circuitry being mounted on a tape carrier package, as recited for example in Japanese Patent Laid-Open No. 3684/1994.
Additionally, the related art technique for transferring in driver circuitry of the digital signal sequential transfer scheme type a polarity-inverted signal to a driver circuit of the next stage in order to cancel any possible variation or deviation of the duty ratio of a signal is disclosed in SHARP Technical Bulletin, No. 74 (August in 1999) at pp. 31-34. Any one of the above-cited related art references fails to teach nor suggest in any way a clock compensation circuit for making the rise-up timing of a clock signal identical to the fall-down timing thereof.
As shown in FIG. 32A, in the case of so-called dual edge accept/import scheme for receiving and taking thereinto—say, accepting or “importing”—display data both at the rise-up time point of a display data accepting clock signal and the fall-down point thereof, it should be required that the riseup point and falldown point of such clock signal be identical to an intermediate time point of changeover time of display data in order to provide a margin or “clearance” to a setup period and a hold period.
However, with liquid crystal display devices of the type which employ the above-stated digital signal sequential transfer scheme, any display data and clock signal(s) as sent out of a timing controller (or alternatively display control device) are expected to propagate over signal lines within respective driver circuits and transfer lines between respective driver circuits (transfer lines on a glass substrate or those on a tape carrier package).
In other words, the display data and clock signal(s) as sent out of the timing controller will be delivered and passed between respective drain drivers in a one-by-one manner.
For this reason, the duty ratio of a clock signal (namely, the ratio of a “High” level period to the cycle or period of a pulse signal) can deviate due to a variation in the internal characteristics of each drain driver—e.g., threshold voltage (Vth) of each MOS transistor in a CMOS inverter circuit—and/or some factors on transfer lines; and simultaneously, a plurality of repeated signal receive-and-pass events would result in such duty ratio variations being accumulated unwantedly.
And, if the clock signal's duty ratio variation increases causing the resultant phase difference relative to display data to increase accordingly, as shown in FIG. 32B, either the setup period or the hold period in the case of accepting display data in response to a clock signal decreases: in the worst case, it will become impossible to accept any display data at each driver circuit, which leads to occurrence of erroneous display on the liquid crystal display panel, resulting in an appreciable decrease in display quality.
Although the problems discussed above become more remarkable in the case of the scheme for accepting display data at both edges of a clock signal, similar problems might occur in the case of schemes for accepting display data at either one edge of the clock signal.